#ifndef icrdefs_h_20040513125411
#define icrdefs_h_20040513125411

#define CORE_ADDR_BASE(core_id)	(0x80000000 | (core_id) << 28)

#define ICR_ADDRESS_CORE(core_id) (0x0FC00000U + CORE_ADDR_BASE(core_id))
#define ICR_ADDRESS_LOCAL() ICR_ADDRESS_CORE((__sb_cfsr(MACH_THID) >> 4) & 0x7)

/** PSDA or PSDB **/
#define ICR_ADDRESS_CORE_CHANNEL(core, channel)	(ICR_ADDRESS_CORE(core) + channel)

#define ICR_GET(base, reg) (*(volatile unsigned*)((base) + (reg)))
#define ICR_SET(base, reg, val) (*(volatile unsigned*)((base) + (reg))=(val))

/*
 * Analog-to-Digital DMA channel control registers
 */
#define REG_A2DISTR 0x8
#define REG_A2DQSTR 0x10
#define REG_A2DCTL  0x18

#define A2D_CTL_DISABLE        0
#define A2D_CTL_ENABLEI        0x80000000
#define A2D_CTL_ENABLEQ        0x40000000
#define A2D_CTL_DECIMATION(n)  (((n)&3)<<28)
#define A2D_CTL_TIMER(x)       (((x)&7)<<15)
#define A2D_CTL_BUFSIZE(n)     (((n)&0x3FFC)<<1)
#define A2D_CTL_BUFCOUNT(n)    (((n)&0xFF)<<20)

#define MMIO_SB3500D2A_A_OFF    0x0040
#define MMIO_SB3500D2A_B_OFF    0x1040
#define MMIO_SB3500A2D_A_OFF    0x0000
#define MMIO_SB3500A2D_B_OFF    0x1000
#define MMIO_SB3500PSDA_EN      0x2480
#define MMIO_SB3500PSDB_EN      0x2488
#define MMIO_SB3500PSDA_STATUS  0x2400
#define MMIO_SB3500PSDB_STATUS  0x2408

/** Until sbsim is fixed **/
#ifdef RUN_ON_BOARD
#define MMIO_SB3500PSDB_INT     29
#define MMIO_SB3500PSDA_INT     28
#else
#define MMIO_SB3500PSDB_INT     29//21
#define MMIO_SB3500PSDA_INT     28//20
#endif

/*
 * Digital-to-Analog DMA channel control registers
 */
#define REG_D2AISTR 0x8
#define REG_D2AQSTR 0x10
#define REG_D2ACTL  0x18

#define D2A_CTL_DISABLE       A2D_CTL_DISABLE
#define D2A_CTL_ENABLEI       A2D_CTL_ENABLEI     
#define D2A_CTL_ENABLEQ       A2D_CTL_ENABLEQ     
#define D2A_CTL_DECIMATION(n) A2D_CTL_DECIMATION(n)
#define D2A_CTL_TIMER(x)      A2D_CTL_TIMER(x)     
#define D2A_CTL_BUFSIZE(n)    A2D_CTL_BUFSIZE(n)   
#define D2A_CTL_BUFCOUNT(n)   A2D_CTL_BUFCOUNT(n)

#endif


